Japanese Patent Application No. 2001-255993 filed on Aug. 27, 2001, and Japanese Patent Application No. 2001-342201 filed on Nov. 07, 2001, are hereby incorporated by reference in their entirety.
The present invention relates to an electron beam test system and an electron beam test method, and particularly relates to an electron beam test system and an electron beam test method can judge high/low potentials with respect to a DC signal and a signal having no change in potential from the previous time of timing to be observed.
FIG. 4 is a constructional view showing a conventional electron beam test system.
The electron beam test system 100 has an electron beam prober 101, a high accuracy LSI tester 102 for operating a device connected to this electron beam prober 101, a control EWS (engineering work station) 106 for controlling operations of the electron beam prober 101 and the high accuracy LSI tester 102.
The electron beam prober 101 has a structure constructed such that a beam blanker 103 for forming a pulse beam, an analytical grid 104 for observing a potential distribution and measuring a waveform, and a waveform measuring unit 105 connected to this analytical grid 104 are added to a SEM (scanning electron microscopy). A fixing stage 109 for placing a semiconductor wafer is arranged on an X-Y moving stage 108.
A non-defective or defective semiconductor wafer (semiconductor integrated circuit device) is placed on the fixing stage 109.
This semiconductor wafer is connected to a test head 110, and is operated by this test head 110. In other words, a predetermined test pattern signal including a clock signal is inputted from the test head 110 to each input terminal of the semiconductor wafer.
An electron beam is irradiated by a field emission gun (FE-Gun) 107 to the operated semiconductor wafer through the beam blanker 103.
A secondary electron from the semiconductor wafer is detected by a secondary electron detector 111 through the analytical grid 104, and a voltage waveform of the operated semiconductor wafer, etc. are measured by the waveform measuring unit 105.
FIG. 5 shows one example of the test pattern signal supplied to the semiconductor wafer and its measured waveform. Here, one example of a clock signal waveform of wiring of the semiconductor wafer and a differential waveform appearing on a passivation film is shown.
As shown in this figure, the differential waveform appearing on the passivation film is detected in the voltage waveform measurement in the electron beam test system. In timing in which the test pattern signal supplied to the semiconductor wafer becomes a pattern signal to be observed, a clock period is lengthened and a potential contract image at an arbitrary time is taken in.
In the above conventional electron beam test system, the image of a low potential becomes light and the image of a high potential becomes dark in a pulse signal such as a clock signal. Accordingly, the observation can be made similarly to a state having no passivation film even when no passivation film is separated.
However, in the conventional technique, the image becomes gray (intermediate color) with respect to the DC (direct current) signal and a signal having no change in potential from the previous time of timing to be observed. Therefore, no high/low potentials can be judged so that it is difficult to recognize the potential.
Further, in the conventional technique, the processing of taking in the potential contrast is performed every time the predetermined desirable test pattern signal is inputted while the test pattern is looped. Accordingly, it is necessary to set plural shots in which the potential contrast is taken in every time the test pattern is looped. The obtained plural potential contrasts were integrated, and the final potential contrast image was generated.
Accordingly, in the conventional technique, it takes time to generate the image of the potential contrast. As a result, a problem exists in that faulty or breakdown caused by process results cannot be rapidly analyzed.
In addition, in such a conventional technique, a problem exists in that no defective phenomenon having no repeating reproducibility can be observed.
In consideration of the above problems, the present invention may provide an electron beam test system and an electron beam test method capable of obtaining potential information of the semiconductor integrated circuit device by observing one phenomenon, and judge high/low potentials with respect to the DC signal and a signal having no change in potential from the previous time of timing to be observed.
(1) One aspect of the present invention relates to an electron beam test system which obtains a potential contrast for analysis by irradiating an electron beam to a semiconductor integrated circuit device to be analyzed.
This electron beam test system comprises:
a tester which supplies a test pattern signal for analysis to the semiconductor integrated circuit device to be analyzed, and holds the test pattern signal at a given timing, and then changes a potential of a direct current power source of the semiconductor integrated circuit device to be analyzed and a potential of the held test pattern signal to a reference potential; and
a detector which takes in the potential contrast right after the reference potential is set.
This electron beam system adopts a construction in which the test pattern signal in timing to be observed is held for a predetermined time, and this held test pattern signal (input signal) and the direct current power source potential are changed to the reference potential. When the held test pattern signal, etc. are changed to the reference potential, the signal to be observed can be detected as a differential waveform by adopting this construction even when this signal to be observed is a DC (direct current) signal and a signal having no change in potential from the previous time of timing to be observed.
As mentioned above, a high or low potential can be also judged with respect to the DC signal and the signal having no change in potential from the previous time of the timing to be observed.
In addition, in accordance with the present invention, a potential of a signal line can be detected as an attenuation signal on a passivation film. Therefore, the generation of a preferable potential contrast image can be realized by the observation of one phenomenon (the observation of a single shot phenomenon) without looping the test pattern signal. Namely, the potential contrast image can be generated by observing the single shot operating phenomenon of the attenuation of a waveform. Therefore, it is possible to realize a system capable of simply obtaining potential information in the single shot observed from above the passivation film of the semiconductor integrated circuit device.
(2) This electron beam system may further include:
an electron gun which irradiates the electron beam to the semiconductor integrated circuit device to be analyzed; and
an analytical grid for observing a potential distribution, which is arranged between the electron gun and the semiconductor integrated circuit device to be analyzed.
(3) This electron beam system may further include a stage for placing the semiconductor integrated circuit device to be analyzed, and freely and horizontally movable.
(4) Another aspect of in the present invention relates to an electron beam test system which obtains a potential contrast for analysis by irradiating an electron beam to a semiconductor integrated circuit device to be analyzed.
This electron beam test system comprises:
a first stage for placing the semiconductor integrated circuit device to be analyzed;
a second stage for placing a non-defective semiconductor integrated circuit device for comparison with the semiconductor integrated circuit device to be analyzed;
a tester which supplies a test pattern signal for analysis to each of the semiconductor integrated circuit device to be analyzed and the non-defective semiconductor integrated circuit device, and holds the test pattern signal at a given timing, and then performs an operation of changing a potential of a direct current power source of each of the semiconductor integrated circuit device to be analyzed and the non-defective semiconductor integrated circuit device and a potential of the held test pattern signal to a reference potential;
a first detector which takes in the potential contrast of the semiconductor integrated circuit device to be analyzed right after the reference potential is set; and
a second detector which takes in the potential contrast of the non-defective semiconductor integrated circuit device right after the reference potential is set.
In accordance with this electron beam test system, the potential contrast of the semiconductor integrated circuit device to be analyzed can be compared with the potential contrast of the non-defective semiconductor integrated circuit device. Thus, an analytic time can be greatly shortened.
(5) This electron beam system may further include:
a first electron gun which irradiates the electron beam to the semiconductor integrated circuit device to be analyzed;
a second electron gun which irradiates the electron beam to the non-defective semiconductor integrated circuit device;
a first analytical grid for observing a potential distribution, which is arranged between the first electron gun and the first stage; and
a second analytical grid for observing the potential distribution, which is arranged between the second electron gun and the second stage.
(6) A further aspect of the present invention relates to an electron beam test system which obtains a potential contrast by irradiating an electron beam to a semiconductor integrated circuit device to be analyzed,
wherein a test pattern signal supplied to the semiconductor integrated circuit device to be analyzed is held at a given timing, and a potential of a direct current power source of the semiconductor integrated circuit device to be analyzed and a potential of the held test pattern signal are then changed to a reference potential, and the potential contrast of the semiconductor integrated circuit device to be analyzed right after the change is taken in.
(7) A still further aspect of the present invention relates to an electron beam test system which irradiates an electron beam to a semiconductor integrated circuit device to be analyzed and a non-defective semiconductor integrated circuit device for comparison with the semiconductor integrated circuit device to be analyzed, and obtains a potential contrast from each of the semiconductor integrated circuit device to be analyzed and the non-defective semiconductor integrated circuit device, the electron beam test system comprising:
holding a test pattern signal supplied to each of the semiconductor integrated circuit device to be analyzed and the non-defective semiconductor integrated circuit device at a given timing, and then performing an operation of changing a potential of a direct current power source of each of the semiconductor integrated circuit device to be analyzed and the non-defective semiconductor integrated circuit device and a potential of the held test pattern signal to a reference potential; and
taking in the potential contrast of the semiconductor integrated circuit device to be analyzed right after the reference potential is set, and taking in the potential contrast of the non-defective semiconductor integrated circuit device right after the reference potential is set.
(8) In the electron beam system according to these aspects of the present invention, the reference potential may be a ground potential.
Namely, when the potential of an electrode is changed from the high potential to the low potential (ground potential) on the actual passivation film, it is confirmed that the potential holding time of a subsequently generated attenuation waveform is approximately twice the hold time of the test pattern signal in comparison with the reverse case. Accordingly, a sufficiently long attenuation time can be obtained by setting the reference potential to the ground potential. The potential information can be obtained in more detail and faulty or breakdown caused by a process result of the semiconductor integrated circuit device can be more reliably detected by utilizing this sufficiently long attenuation period.
(9) The electron beam system according to these aspects of the present invention may include a beam control section which irradiates the electron beam to the semiconductor integrated circuit device as frame scan irradiation, and controls the electron beam so that the frame scan irradiation is performed during at least a hold period of the test pattern signal and a taking-in period of the potential contrast.
The potential of the passivation film surface of the surface of the semiconductor integrated circuit device is initialized by charging by frame-scan-irradiating the electron beam during the hold period of the supply test pattern signal. The attenuation waveform can be also reliably generated by frame-scan-irradiating the electron beam during the taking-in period of the potential contrast after the held signal potential is changed to the reference potential.
(10) The electron beam system according to these aspects of the present invention may include a contrast image generating section which sequentially takes in the potential contrast plural times during an attenuation period of the potential contrast right after the reference potential is set, and integrates a plurality of taken in potential contrasts in accordance with a given rule to generate a potential contrast image.
The potential of a signal line can be detected as a large attenuation signal on the passivation film by changing the held test pattern signal to the reference potential. Therefore, the present invention adopts a construction in which the potential contrast is sequentially taken in plural times during this attenuation period, and the plural taken in potential contrasts are integrated in accordance with the predetermined rule, and the potential contrast image is generated. Thus, the generation of a more preferable potential contrast image consistent in the strength of the potential contrast and an S/N ratio can be realized by the observation of a single shot phenomenon. Namely, it is possible to realize a system in which the single shot phenomenon of attenuation of a waveform is observed, and the potential information of the semiconductor integrated circuit device can be obtained simply and more reliably in the single shot observed from above the passivation film.
Further, in the electron beam system according to these aspects of the present invention, the potential contrast image may be generated by setting an integration ratio of the potential contrast taken in earliest to be greater than an integration ratio of the potential contrast taken in after the earliest potential contrast.
Thus, it is possible to optimize an image storing ratio to a memory means (e.g., frame memory) of the plural taken in potential contrasts. Accordingly, it is possible to generate the potential contrast image in which the potential contrast strength and the S/N ratio are further optimized.
(11) In the electron beam system according to these aspects of the present invention, timing for changing a potential of the direct current power source and a potential of the held test pattern signal to the reference potential and start timing of taking in the potential contrast may be determined in connection with a start of holding the supplied test pattern signal.
It is sufficient to firstly set the timing for changing the potential to the reference potential and the start timing of taking in the potential contrast only once by adopting the above construction. Thereafter, when the product kind of the semiconductor integrated circuit device to be analyzed is changed and the timing of the test pattern signal to be observed is further changed, it is not necessary to reset the timing for changing the potential to the reference potential and the start timing of taking in the potential contrast so that the entire system is very simply treated.
The following construction for generating the above trigger signal can be also adopted when it is assumed as one example of such a construction that a system portion for supplying the test pattern signal to the semiconductor integrated circuit device and a system portion for taking in the potential contrast by irradiating the electron beam to the semiconductor integrated circuit device are separately formed in hardware in the system.
In the system portion which supplies the test pattern signal, as one example of the above system,
a trigger signal may be generated in connection with a start of holding the supplied test pattern signal, and a potential of the direct current power source and a potential of the held test pattern signal may be changed to the reference potential after a predetermined hold time has passed, and
in the system portion for taking in the potential contrast,
timing of vertical scanning for image taking-in may be reset after a predetermined delay time has passed from the generation of the trigger signal, and the potential contrast may begin to be taken in synchronously with timing of termination of a predetermined number of times of the vertical scanning after the reset, and
the predetermined delay time may be set to a value at which timing of the termination of the predetermined number of times of the vertical scanning after the reset is conformed to timing of passing the hold time.
In the system portion which supplies the test pattern signal, as one example of the above system,
a trigger signal may be generated in connection with a start of holding the supplied test pattern signal, and a potential of the direct current power source and a potential of the held test pattern signal may be changed to the reference potential after a predetermined hold time has passed, and
in the system portion for taking in the potential contrast,
timing of vertical scanning for image taking-in may be reset after a predetermined delay time has passed from the generation of the trigger signal, and the potential contrast may begin to be taken in, and
the predetermined delay time may be set to a value at which timing for resetting the vertical scanning is conformed to timing of passing the hold time.
It is sufficient to firstly set the start timing of taking in the potential contrast only once in conformity with the generation of the trigger signal by adopting the above construction even in the system in which a system portion for supplying the test pattern signal to the semiconductor integrated circuit device and a system portion for taking in the potential contrast by irradiating the electron beam to the semiconductor integrated circuit device are separately formed in hardware. Further, thereafter, when the product kind of the semiconductor integrated circuit device to be analyzed is changed and the timing of the test pattern signal to be observed is further changed, it is not necessary to reset the timing for changing the potential to the reference potential and the start timing of taking in the potential contrast so that the entire system can be very simply treated.
(12) An even further aspect of the present invention relates to an electron beam test method, comprising:
holding a test pattern supplied to a semiconductor integrated circuit device to be analyzed for a predetermined time in timing to be observed, and then changing a direct current power source of the semiconductor integrated circuit device to be analyzed and the held test pattern signal to a reference potential, and irradiating an electron beam to the semiconductor integrated circuit device to be analyzed; and
generating a potential contrast image for analyzing faulty or breakdown caused by a process defect by taking in the potential contrast right after the change to the reference potential.
(13) A yet further aspect of the present invention relates to an electron beam test method, comprising:
holding a test pattern supplied to a semiconductor integrated circuit device to be analyzed for a predetermined time in timing to be observed, and then changing a direct current power source of the semiconductor integrated circuit device to be analyzed and the held test pattern signal to a reference potential, and irradiating an electron beam to the semiconductor integrated circuit device to be analyzed, and holding the test pattern supplied to a non-defective semiconductor integrated circuit device for comparison with the semiconductor integrated circuit device to be analyzed for a predetermined time in timing to be observed, and then changing a direct current power source of the non-defective semiconductor integrated circuit device and the held test pattern signal to the reference potential, and irradiating the electron beam to the non-defective semiconductor integrated circuit device; and
generating a potential contrast image of each of the semiconductor integrated circuit device to be analyzed and the non-defective semiconductor integrated circuit device by taking in the potential contrast of each of the semiconductor integrated circuit device to be analyzed and the non-defective semiconductor integrated circuit device right after the change to the reference potential, and analyzing faulty or breakdown caused by a process defect of the semiconductor integrated circuit device to be analyzed by comparing the potential contrast image of each of the semiconductor integrated circuit device to be analyzed and the non-defective semiconductor integrated circuit device.
(14) The electron beam test method according to these aspects of the present invention may include irradiating the electron beam to the semiconductor integrated circuit device as frame scan irradiation, and performing the frame scan irradiation during at least a hold period of the test pattern signal to be supplied and a taking-in period of the potential contrast.
(15) The electron beam test method according to these aspects of the present invention may include sequentially taking in the potential contrast plural times during an attenuation period of the potential contrast right after the reference potential is set, and integrating a plurality of taken in potential contrasts in accordance with a given rule to generate a potential contrast image.
(16) Further, in these aspects of the present invention, the semiconductor integrated circuit device may be analyzed in a state of simplex. The semiconductor integrated circuit device may be analyzed in a state of a semiconductor wafer in which the semiconductor integrated circuit device is formed. Further, the semiconductor integrated circuit device may be analyzed in the both states.
(17) Further, in these aspects of the present invention, a potential of the direct current power source of the semiconductor integrated circuit device and a potential of the test pattern signal may be directly changed to the reference potential without holding the test pattern signal in timing in which the test pattern signal supplied to the semiconductor integrated circuit device becomes a test pattern signal to be observed, and the potential contrast may be taken in right after the change to the reference potential.